Senior Digital Design-Physical Implementation Engineer (IP)

Pracovní nabídka

onsemi’s Central IP division is responsible for the design, verification, integration and support of reusable intellectual property (IP) that then facilitates custom ASIC and ASSP developments.

Currently, we have an opening for a digital design engineer focusing on physical implementation. This position is in the IP team in our Brno, Czech Republic. We are searching for senior candidates but considering juniors, too, willing to develop their physical implementation knowledge.

Responsibilities:

- Process RTL through implementation phases (synthesis, DFT, STA, P&R)

• Design intent (power intent/UPF, timing constraints/SDC)
• DFT and ATPG
• Floorplanning & power grid design
• Clock tree synthesis
• Timing closure

- Perform post-layout sign-off checks

• Parasitics extraction
• Timing analysis
• Power analysis
• Physical verification (DRC, LVS, ANT)

- Submit GDS for Tape-In, contribute to Tape-Out activities

Qualification:

• willingness to specialize in physical implementation
• knowledge of some synthesis, DFT, STA and/or place & route tools
• HDL language knowledge – Verilog, SystemVerilog or VHDL
• experience with FPGA, ASIC or ASSP development flow
• scripted programming skills – Tcl preferred, Perl or Python is a plus
• written and verbal communication skills in English (technical topics)
• university degree in Electrical Engineering or Information Technology
• open mind with willingness to learn and apply new skills and concepts
• experience with functional verification and simulation is a plus