Senior Verification Engineer

Responsibilities:

* Architect logically complex digital verification environments.
* Developing SystemVerilog/UVM testbenches for block and SoC level functional verification.
* Developing detailed verification plans for block/SoC.
* Debugging and correcting functional errors in the RTL, using simulation tools, debug tools, and programming skills.
* Defining and implementing functional coverage, and enhancing the testbench to ensure coverage closure.
* Documenting test plans and testbench design.
* Lead project teams and mentor junior team members.

Requirements:

* BS degree in Electrical Engineering or related field
* 10 years of digital verification experience
* Sound knowledge of Verilog or System Verilog
* Experience with verification methodologies e.g. UVM
* Experience with scripting language like Python/Perl
* Good command of English
* Self-motivated with the ability to work independently and interface effectively with team members in a remote location
* Experience with high-speed interfaces, such as DDR, PCIe or MIPI, is an advantage

Location:

Bratislava

Customer Category:

Engineering